发明名称 |
その側壁での窒素濃度が高められたSiONゲート誘電体を含むMOSトランジスタ |
摘要 |
A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is >= the N concentration in a bulk of the annealed N-enhanced SiON gate layer -2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack. |
申请公布号 |
JP6027531(B2) |
申请公布日期 |
2016.11.16 |
申请号 |
JP20130523328 |
申请日期 |
2011.08.04 |
申请人 |
日本テキサス・インスツルメンツ株式会社;テキサス インスツルメンツ インコーポレイテッド |
发明人 |
ブライアン ケイ カークパトリック;ジェームズ ジェイ チェンバーズ |
分类号 |
H01L21/336;H01L21/28;H01L21/318;H01L29/423;H01L29/49;H01L29/78 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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