| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory device that efficiently executes read processing of a slow speed and large capacity flash memory on the basis of an effective flag to be set for each one page unit of cache.SOLUTION: A semiconductor memory device according to an embodiment comprises: a CPU; a slow speed and large capacity flash memory; a cache memory storing a part of data stored in the flash memory; a host interface controlling the access of the cache memory; and control means. The control means has a flag register in which the CPU sets a flag indicating an effective bit when data from a host or data from the flash memory is written, and otherwise indicating a non-effective bit, and rewrites the content of the cache memory only in a sector in which the content of the flag register indicates the non-effective bit when data of each page is copied from the flash memory to the cache memory. Rewritten data in a plurality of pages of the cache memory after completing of the copy is written back to the flash memory. |
