| 摘要 |
PROBLEM TO BE SOLVED: To provide a cache memory capable of reducing a working voltage of the whole cache memory.SOLUTION: The cache memory includes; a data storage structure including tags; and a plurality of cache ways including blocks of a plurality of memory cells. The block comprises: a memory cell including a pair of cross coupled inverters connected to a path continuing to each of a pair of bit lines each having an output arranged corresponding to a column of the memory cells, a pair of switch parts provided between the bit line and an output of the inverter, and a word line controlling conduction of the switch part; and a mode control line controlling the conduction of a mode control switch part provided between data holding nodes of the adjacent memory cells. The cache memory is further provided with a circuit allowing switching to a high reliability mode by coupling two memory cells for each block. When a failure of the block is detected, the detected block is switched to the high reliability mode to increase the operation margin of the failure block. |
