PHASE CORRECTION IN A DOHERTY POWER AMPLIFIER

摘要

In various embodiments, a semiconductor package includes a carrier amplifier (506) connected to a first output of a power divider(504), and a first output matching network (514) connected to the carrier amplifier(506) and an output combining node (510). The first output matching network (514) exhibits a phase delay during operation of the carrier amplifier (506). The semiconductor package includes a phase advance network (516) connected to the first output matching network (514). The phase advance network (516) is configured to offset at least a portion of the phase delay of the first output matching network (514). The semiconductor package includes a peaking amplifier (508) connected to a second output of the power divider (504) and the output combining node (510), and a second output matching network (520) connected to the peaking amplifier (508).