| 摘要 |
Multiple master modules are connected to a bus, each having bus communication logic for initiating a transaction over the bus. The bus communication logic is able to detect when the bus is busy (or apparently busy), and in response will wait before initiating a transaction of its own. Further, a distributed reset sub-system is provided, comprising an instance of a reset mechanism at each of a plurality of the master modules. Each reset mechanism recognizes a timeout condition indicative of the detected busy state being due to error, and in response performs a staged reset. This reset process first attempts a local reset which resets the respective bus communication logic of its respective master module. If the local reset fails to clear the error, the staged reset process then attempts one or more further resets to reset bus communication logic of one or more other modules connected to the bus. |
