发明名称 Via Definition Scheme
摘要 A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is grown over the metal pattern layer and the first dielectric layer. A metal trench is formed with a metal width in the first dielectric layer. A via hole is formed with a via width in the second dielectric layer.
申请公布号 US2016329240(A1) 申请公布日期 2016.11.10
申请号 US201615217623 申请日期 2016.07.22
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Lu Yen-Cheng;Shih Chih-Tsung;Yu Shinn-Sheng;Chen Jeng-Horng;Yen Anthony
分类号 H01L21/768;H01L21/033;H01L21/311 主分类号 H01L21/768
代理机构 代理人
主权项 1. A method, comprising: defining a conductive line pattern layer over a first dielectric layer, wherein the first dielectric layer is disposed over a second dielectric layer, and wherein an opening in the conductive line pattern layer exposes a first portion of the first dielectric layer, the first portion having a first width; forming spacers along sidewalls of the opening, wherein after forming the spacers a second portion of the first dielectric layer is exposed, the second portion of the first dielectric layer having a second width; etching the second portion of the first dielectric layer using the spacers as a mask to expose a portion of the second dielectric layer; removing the spacers after etching the second portion of the first dielectric layer, the removing exposing third portions of the first dielectric layer; etching the third portions of the first dielectric layer to form a trench in the first dielectric layer, the trench having the first width; and etching the portion of the second dielectric layer to form a via hole in the second dielectric layer, the via hole having the second width.
地址 Hsin-Chu TW