| 发明名称 |
CIRCUIT AND METHOD FOR REDUCING AN OFFSET COMPONENT OF A PLURALITY OF VERTICAL HALL ELEMENTS ARRANGED IN A CIRCLE |
| 摘要 |
Output signals from two or more vertical Hall elements arranged in a circle are combined is ways that reduce an offset voltage as the two or more vertical Hall elements are sequenced to generated a sequential output signal. |
| 申请公布号 |
EP3090271(A1) |
申请公布日期 |
2016.11.09 |
| 申请号 |
EP20140825568 |
申请日期 |
2014.12.23 |
| 申请人 |
ALLEGRO MICROSYSTEMS, LLC |
发明人 |
ROMERO, HERNAN, D. |
| 分类号 |
G01R33/07 |
主分类号 |
G01R33/07 |
| 代理机构 |
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