| 摘要 |
A data processing system 4 includes mapping circuitry (e.g. a translation look-aside buffer 6) storing mapping data entries 10 indicative of virtual-to-physical address mappings for different regions of physical addresses. A hint generator 20 coupled to the mapping circuitry (e.g. the TLB 6) generates hint data in dependence upon the storage of mapping data entries within the mapping circuitry. The hint generator 20 generates hint data dependent upon storage of mapping data entries within the mapping circuitry, for example it may track the loading of mapping data entries and the eviction of mapping data entries from the translation lookaside buffer 6. The hint data is supplied to a memory controller 8 which controls how data corresponding to respective different regions of physical addresses is stored within a heterogeneous memory system, e.g. the power state of different portions of the memories storing different regions, which type of memory is used to store different regions. The hint generating circuitry may further comprise a victim cache to store, for a predetermined threshold time, data entries evicted from the TLB. |
