发明名称 半導体装置の作製方法
摘要 An object is to realize low power consumption while manufacturing a semiconductor device including a thin film transistor whose parasitic capacitance is reduced. Part of an insulating layer covering the periphery of a gate electrode layer is formed to be thick. Specifically, a stack including a spacer insulating layer and a gate insulating layer is formed. The thick part of the insulating layer covering the periphery of the gate electrode layer reduces parasitic capacitance formed between the gate electrode layer of the thin film transistor and another electrode layer (another wiring layer) overlapping with the gate electrode layer.
申请公布号 JP6019159(B2) 申请公布日期 2016.11.02
申请号 JP20150079961 申请日期 2015.04.09
申请人 株式会社半導体エネルギー研究所 发明人 山崎 舜平;坂倉 真之;小山 潤;及川 欣聡;丸山 穂高;神長 正美;岡崎 健一
分类号 H01L21/336;C23C16/42;H01L21/316;H01L21/318;H01L21/8234;H01L27/08;H01L27/088;H01L29/786 主分类号 H01L21/336
代理机构 代理人
主权项
地址