发明名称 半導体集積回路
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of suppressing a decrease in voltage of a signal path connected to a capacitor due to parasitic capacitance.SOLUTION: A semiconductor integrated circuit comprises: a first signal path 21 connected to a first circuit 31; a first electrode 11 connected to the first signal path 21; a capacitor 10 having a second electrode 12 facing the first electrode 11; a second signal path 22 connected to a second circuit 32 connected to the second electrode 12; and a shield part 40 connected to the first signal path 21 and for shielding the second signal path 22 excluding the second electrode 12.
申请公布号 JP6019852(B2) 申请公布日期 2016.11.02
申请号 JP20120156893 申请日期 2012.07.12
申请人 ミツミ電機株式会社 发明人 井上 文裕
分类号 H01L21/822;H01L21/82;H01L27/04 主分类号 H01L21/822
代理机构 代理人
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