发明名称 半導体装置の設計方法及びプログラム
摘要 PROBLEM TO BE SOLVED: To suppress an instantaneous voltage drop in a scan test.SOLUTION: A method of designing a semiconductor includes the steps of: performing arrangement and wiring of a plurality of power supply wirings vss1-vss3, vdd1, and vdd2 and a plurality of scan flip-flops 1-9; detecting the number of scan flip-flops that are connected to a first power supply wiring which is included in the plurality of power supply wirings vss1-vss3, vdd1, and vdd2, on the basis of arrangement information obtained by the arrangement and wiring; generating a plurality of clock signals having different phases on the basis of the detected number of scan flip-flops; and assigning the plurality of clock signals having different phases to the plurality of scan flip-flops 1-9.
申请公布号 JP6015456(B2) 申请公布日期 2016.10.26
申请号 JP20130004318 申请日期 2013.01.15
申请人 株式会社ソシオネクスト 发明人 柴本 亘;荒川 利夫
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04 主分类号 G06F17/50
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