POWER EFFICIENT PROCESSOR ARCHITECTURE

摘要

In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

主权项

1. A processor comprising:
a first plurality of cores; a second plurality of cores, a core of the second plurality of cores having a lower power consumption when in operation than a core of the first plurality of cores; an interconnect coupled to the first plurality of cores and coupled to the second plurality of cores; and a shared cache memory coupled to at least the first plurality of cores; wherein, based at least in part on a performance requirement, an execution state is to be transferred from the core of the second plurality of cores to the core of the first plurality of cores to enable the core of the first plurality of cores to execute an operation.