| 摘要 |
A processor for processing digital data includes at least one butterfly operator for executing an FFT/IFFT computation. This butterfly operator contains a first stage of complex multiplication and a second stage of complex addition and subtraction. Each of these two stages contains a plurality of addition/subtraction hardware modules and data transmission links between these modules. At least a part of the addition/subtraction modules of each stage of the butterfly operator and at least a part of the links between these modules are configurable with the aid of at least one programmable parameter, between a first configuration in which the butterfly operator carries out said fast Fourier transform computation and a second configuration in which the butterfly operator carries out a computation of branch metrics values and of path metrics and survivors values of a Viterbi algorithm. |
