| 摘要 |
A way enable table 210 is provided in a multi-threaded processor and stores an index to an n-way set associative cache. The way enable table 210 comprises one entry 212 for each entry 205 in the cache 202. Each entry in the way enable table is arranged to store a thread ID. A thread ID is the ID of the thread associated with a data item 205 stored in the corresponding entry in the cache 202. Prior to reading entries from the cache identified by an index parameter, the ways in the cache are selectively enabled by way enabling logic 214 based on a comparison of the current thread ID and the thread IDs stored in entries in the way enable table which are identified by the same index parameter. Thus, way enabling hardware logic 214 selectively enables or disables one or more ways of the cache so that disabled or non-enabled ways are not powered up to be read, saving power. The index parameter may be a subset of the bits of a memory location for a data cache or a subset of the bits of a program counter for an instruction cache. |
