| 摘要 |
Methods, apparatuses, and systems are described related a data receiver circuit having a pair of offset edge samplers to sample a data signal, at an edge sampling time between data samples, with respect to different reference levels. A clock-data recovery (CDR) circuit of the receiver circuit may determine an A-count that corresponds to a number of times the signal level of the data signal at the edge sampling time is between the reference levels of the offset edge samples to provide a signal integrity metric for the receiver circuit. The CDR circuit may dynamically update its settings based on the A-count. |
