发明名称 |
Serial-to-parallel conversion circuit and method of designing the same |
摘要 |
The invention eliminates a race condition without restricting reception speed. The invention provides a method of designing a serial-to-parallel conversion circuit, the method including determining a rule for data (D) and a strobe (S) when a first-stage memory device (10a,20a) in a shift register (SF1,SF2) latches data and when the memory device holds the data; providing a logical circuit (30,40) for generating an output conforming to the rule at a data input side of the shift register; and shifting a data latch timing of the memory device by a half-period. |
申请公布号 |
EP2015457(B1) |
申请公布日期 |
2016.10.19 |
申请号 |
EP20080160241 |
申请日期 |
2008.07.11 |
申请人 |
MITSUBISHI HEAVY INDUSTRIES, LTD. |
发明人 |
ISHII, SHIGERU;NOMACHI, MASAHARU |
分类号 |
H03M9/00;G06F13/42;H04L12/40 |
主分类号 |
H03M9/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|