发明名称 Variable length execution pipeline having an odd number of stages
摘要 A method of scheduling computation in a pipelined computation unit 50 having a pipeline with an odd number of stages 57 to produce an intermediate result 65 for use in an iterative process, comprises: identifying a set of one or more instructions 10 that collectively comprise more discrete portions of computation than the odd number of stages in the pipeline and which comprises a single instruction defining multiple discrete portions of computation, each portion requiring multiple iterations through the pipeline; scheduling each of the multiple discrete portions of computation in the single instruction by staggering each of the discrete portions in the pipeline; adding a wait stage 58 in the pipeline; causing each of the multiple discrete portions to pass through the wait stage, so that each of the portions experiences a latency greater than the odd number of stages in the pipeline; and removing the wait stage from the pipeline in order to process further discrete portions of computation less than or equal to the odd number of stages in the pipeline.
申请公布号 GB2537524(A) 申请公布日期 2016.10.19
申请号 GB20160008809 申请日期 2015.09.23
申请人 Imagination Technologies Limited 发明人 Leonard Rarick;Kristie Veith;Manouk Manoukian
分类号 G06F9/38 主分类号 G06F9/38
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