发明名称 半導体パッケージの製造方法
摘要 When a plating layer is formed on through holes in semiconductor packages, first and second stacked bodies are stacked with first and second cavities formed in the first and second stacked bodies facing the inner side and are bonded together by applying adhesive to peripheral regions so that the cavities of the first and second stacked bodies form sealed spaces, and the through holes are formed such that part of the first and second stacked bodies including the bonding surface remains. Then, the through holes are plated to form the plating layer, the peripheral regions are removed as cutting allowances, i.e., removal regions, and the first and second stacked bodies are divided into a plurality of pieces along dicing lines to form semiconductor packages.
申请公布号 JP6005280(B2) 申请公布日期 2016.10.12
申请号 JP20150524555 申请日期 2014.06.09
申请人 三菱電機株式会社 发明人 二村 政範;竹田 滋紀;立井 芳直;杉浦 勢
分类号 H01L23/12;H01L25/04;H01L25/18 主分类号 H01L23/12
代理机构 代理人
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