发明名称 |
Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data values |
摘要 |
In an embodiment, a fused multiply-add (FMA) circuit is configured to receive a plurality of input data values to perform an FMA instruction on the input data values. The circuit includes a multiplier unit and an adder unit coupled to an output of the multiplier unit, and a control logic to receive the input data values and to reduce switching activity and thus reduce power consumption of one or more components of the circuit based on a value of one or more of the input data values. Other embodiments are described and claimed. |
申请公布号 |
GB2507656(B) |
申请公布日期 |
2016.10.12 |
申请号 |
GB20130018169 |
申请日期 |
2013.10.14 |
申请人 |
Intel Corporation |
发明人 |
Brian J Hickmann;Thomas D Fletcher;Dennis R Bradford |
分类号 |
G06F9/302;G06F1/32;G06F7/483;G06F7/57 |
主分类号 |
G06F9/302 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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