发明名称 電界効果トランジスタ
摘要 This FET includes: a source electrode pad, which is formed on a source electrode and which is electrically connected to the source electrode; and/or a drain electrode pad, which is formed on the drain electrode and which is electrically connected to the drain electrode. The source electrode pad has a cutout for reducing a parasitic capacitance between the source electrode pad and the drain electrode, and the drain electrode pad has a cutout for reducing a parasitic capacitance between the drain electrode pad and the source electrode.
申请公布号 JP6007259(B2) 申请公布日期 2016.10.12
申请号 JP20140545611 申请日期 2013.10.02
申请人 シャープ株式会社 发明人 鈴木 貴光;安藤 隆彦;森下 敏
分类号 H01L21/338;H01L21/3205;H01L21/768;H01L23/522;H01L29/778;H01L29/812 主分类号 H01L21/338
代理机构 代理人
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