| 发明名称 |
DIGITAL SYNCHRONIZER |
| 摘要 |
A digital synchronizer is disclosed, comprising:
a phase locked loop (100) configured to produce an output signal (clkFc) having the same frequency as an input signal (Frx) by selecting a divider ratio (/P) of a frequency divider (130) with a control signal (Pctrl), the frequency divider (130) configured to divide the frequency of a high frequency signal (clkHF) by the divider ratio (/P) to provide the output signal (clkFc);a carrier generator (300) comprising a look-up table (320), the carrier generator (300) configured to generate an oversampled carrier signal using the look-up-table (320) by using the control signal (Pctrl) to produce a carrier signal with a period corresponding with a contemporaneous period of the output signal (clkFc). |
| 申请公布号 |
US2016294541(A1) |
申请公布日期 |
2016.10.06 |
| 申请号 |
US201615085776 |
申请日期 |
2016.03.30 |
| 申请人 |
NXP B.V. |
发明人 |
van de Beek Remco;Verlinden Jos;Al-kadi Ghiath |
| 分类号 |
H04L7/033;H04L29/12;H04B5/00 |
主分类号 |
H04L7/033 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A digital synchronizer, comprising:
a phase locked loop configured to produce an output signal having the same frequency as an input signal by selecting a divider ratio of a frequency divider with a control signal, the frequency divider configured to divide the frequency of a high frequency signal by the divider ratio to provide the output signal; a carrier generator comprising a look-up table, the carrier generator configured to generate an oversampled carrier signal using the look-up-table by using the control signal to produce a carrier signal with a period corresponding with a contemporaneous period of the output signal. |
| 地址 |
Eindhoven NL |
