| 发明名称 |
CLOCK SYNCHRONIZER |
| 摘要 |
Apparatus for clock synchronisation comprising a first phase locked loop (405) and a second phase locked loop (400). The first phase locked loop (405) is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop (405) comprises a frequency divider (428) that controls the multiple in response to a control signal. The second phase locked loop (400) is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (405). The second phase locked loop (400) comprises phase adjustment means (450), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration. |
| 申请公布号 |
US2016294398(A1) |
申请公布日期 |
2016.10.06 |
| 申请号 |
US201615085821 |
申请日期 |
2016.03.30 |
| 申请人 |
NXP B.V. |
发明人 |
Verlinden Jos;van de Beek Remco;Mendel Stefan |
| 分类号 |
H03L7/087;H03L7/18;H04W4/00;H04L7/033;H04B5/00;H03L7/107;H03L7/197 |
主分类号 |
H03L7/087 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. Apparatus for clock synchronisation comprising:
a first phase locked loop configured to receive a reference signal having a reference frequency, and operable to produce an output signal having an output frequency that is a multiple of the reference frequency, the first phase locked loop comprising a frequency divider that controls the multiple in response to a control signal; a second phase locked loop configured to determine a phase error between the output signal and an input signal, and to provide the control signal to the first phase locked loop; wherein the second phase locked loop comprises phase adjustment means, operable to adjust a phase difference between the input and output signal by varying the control signal for a duration. |
| 地址 |
Eindhoven NL |
