DATA FILTERING USING A PLURALITY OF HARDWARE ACCELERATORS

摘要

Techniques are provided for data filtering using hardware accelerators. An apparatus comprises a processor, a memory and a plurality of hardware accelerators. The processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators. The plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators. The hardware accelerators may be field-programmable gate arrays.

主权项

1. A method comprising:
streaming data from a memory to a first one of a plurality of hardware accelerators; filtering the data in the plurality of hardware accelerators utilizing at least one bit vector partitioned across at least two of the plurality of hardware accelerators; and receiving filtered data from a second one of the plurality of hardware accelerators.