METHOD AND APPARATUS FOR A SUPERSCALAR PROCESSOR

摘要

A superscalar processor, for out of order self-timed execution, comprising a plurality of independent self-timed function units, having corresponding instruction queues for holding instructions to be executed by the function unit. The processor further comprising an instruction dispatcher configured for inputting instructions in program counter order; and determining an appropriate function unit for execution of the instruction and a resource management unit configured for monitoring the function units and signaling availability of the appropriate function unit, wherein the dispatcher only dispatches the instruction to the appropriate function unit in response to the availability signal from the resource management unit.

主权项

1. A super scalar processor comprising:
a plurality of parallel self-timed function units; an instruction dispatcher configured to dispatch instructions to function units in a program counter order; and event logic associated with each of the plurality of function units, the event logic configured to trigger operation of its associated function unit to generate an instruction execution result in response to receipt of a dispatched instruction at the function unit, where execution results among the plurality of parallel function units are unconstrained to be generated in program counter order.