MEMORY CONTROLLER INCLUDING HOST COMMAND QUEUE AND METHOD OF OPERATING THE SAME

摘要

Disclosed is a memory controller, including: a host interface suitable for queueing a plurality of host commands from a host in a host command queue; a state register suitable for storing ready set bits respectively corresponding to the plurality of host commands; a memory command generating unit suitable for generating and queueing memory commands and state update information corresponding to the queued host commands in a memory command queue, respectively; and the memory command performing unit suitable for performing an operation in response to the queued memory commands. The memory command performing unit obtains state update information corresponding to the performed memory command from the memory command queue, and updates a ready set bit of a host command corresponding to the performed memory command based on the obtained state update information.

主权项

1. A memory controller, comprising:
a host command queue; a host interface suitable for queueing a plurality of host commands from a host in the host command queue; a state register suitable for storing ready set bits respectively corresponding to the plurality of host commands, wherein each of the ready set bits indicates whether corresponding one of the plurality of host commands is ready and available; a memory command queue; a memory command generating unit suitable for generating and queueing memory commands and state update information in the memory command queue; and the memory command performing unit suitable for performing an operation in response to the queued memory commands, wherein the memory command performing unit obtains state update information corresponding to the performed memory command from the memory command queue, and updates a ready set bit of a host command corresponding to the performed memory command based on the obtained state update information.