| 发明名称 |
STACKED DIE SEMICONDUCTOR DEVICE WITH INTERCONNECT STRUCTURE |
| 摘要 |
An apparatus includes a first tier, a second tier and a memory. The second tier is vertically stacked on the first tier. The memory includes a column of memory bit cells. A first portion of the column of memory bit cells is on the first tier. A second portion of the column of memory bit cells is on the second tier. |
| 申请公布号 |
US2016293227(A1) |
申请公布日期 |
2016.10.06 |
| 申请号 |
US201514673108 |
申请日期 |
2015.03.30 |
| 申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
CHI Shyh-An |
| 分类号 |
G11C5/02;G11C5/06 |
主分类号 |
G11C5/02 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus, comprising:
a first tier; a second tier vertically stacked on the first tier; and a memory comprising a column of memory bit cells, wherein
a first portion of the column of memory bit cells is on the first tier; anda second portion of the column of memory bit cells is on the second tier. |
| 地址 |
Hsinchu TW |
