SYSTEM FOR VERIFYING TIMING CONSTRAINTS OF IC DESIGN

摘要

An EDA tool for verifying timing constraints of an integrated circuit (IC) design includes a processor and a memory that stores register transfer level (RTL) code of the IC design and a timing constraint file. The processor generates a netlist based on the RTL code, and identifies asynchronous clock paths, false paths and multi-cycle paths in the netlist using the timing constraint file. The processor then inserts buffer cells for logic cells in the netlist. The processor also inserts buffer cells in the asynchronous clock paths, false paths, and multi-cycle paths. The processor delay annotates logic cells and clock delay cells with a zero delay value and the buffer cells with known delay values. The processor generates a modeled standard delay format (SDF) file and performs a gate level simulation (GLS) using the modeled SDF file.

主权项

1. An electronic design automation (EDA) tool for verifying timing constraints of a netlist, wherein the netlist is indicative of an integrated circuit (IC) design, the EDA tool comprising:
a memory for storing a register transfer level (RTL) code of the IC design and a timing constraint file, wherein the timing constraint file includes asynchronous clock, false path, and multi-cycle path constraints; and a processor in communication with the memory, wherein the processor is configured for:
generating the netlist based on the RTL code, wherein the netlist includes a plurality of logic cells and a plurality of clock delay cells that form a plurality of clock paths, a plurality of false paths, and a plurality of multi-cycle paths;reading the timing constraint file stored in the memory;inserting a plurality of buffer cells into the netlist, including inserting at least one first buffer cell for each logic cell of the plurality of logic cells in the netlist, wherein the at least one first buffer cell and its corresponding logic cell form a two-stage logic cell;identifying at least one clock path of the plurality of clock paths based on the asynchronous clock constraints;inserting at least one second buffer cell into the at least one clock path;identifying at least one false path of the plurality of false paths based on the false path constraints;inserting at least one third buffer cell into the at least one false path;identifying at least one multi-cycle path of the plurality of multi-cycle paths based on the multi-cycle path constraints;inserting at least one fourth buffer cell into the at least one multi-cycle path;delay annotating the plurality of logic cells and the plurality of clock delay cells with a zero delay value;delay annotating the at least one first, second, third, and fourth buffer cells with first, second, third, and fourth delay values, respectively;generating a modeled standard delay format (SDF) file;storing the modeled SDF file in the memory; andperforming a gate level simulation (GLS) based on the modeled SDF file for verifying the asynchronous clock, false path, and multi-cycle path constraints.