Low Energy Accelerator Processor Architecture with Short Parallel Instruction Word and Non-Orthogonal Register Data File

摘要

Apparatus for a low energy accelerator processor architecture. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory ; a low energy accelerator processor configured to execute instruction words coupled to the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to retrieved instruction words; and a non-orthogonal data register file comprising a set of data registers coupled to the plurality of execution units, the registers coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.

主权项

1. An integrated circuit, comprising:
a system bus for transferring data between memory devices, processors, and peripheral devices having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory coupled to the system bus, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to a selected one of the data width N of the system bus and twice the data width N of the system bus; and a non-orthogonal data register file comprising a set of data registers coupled to the plurality of execution units, the data registers coupled to selected ones of the plurality of execution units being less than all of the data registers in the data register file.