VERTICAL GATE-ALL-AROUND TFET

摘要

A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

主权项

1. A device, comprising:
a silicon substrate; a diode on the substrate, the diode including:
a doped well in the silicon substrate;a nanowire on the substrate extending from the doped well;a first contact is formed on a first end of the nanowire; anda second contact is formed adjacent to a second end of the nanowire, where the second end of the nanowire is adjacent to the doped well.