SHIFT REGISTER UNIT CIRCUIT, SHIFT REGISTER, DRIVING METHOD, AND DISPLAY APPARATUS

摘要

The present disclosure relates to the field of display technology, and discloses a shift register unit circuit, comprising a trigger signal end, a first clock end, a second clock end, a reset end, a gate output end, a low level end, a storage capacitor, a reset module, a first pull-down module, a second pull-down module, a charging module, and an output control module. The present disclosure further discloses a shift register, a driving method, and a display apparatus. The shift register unit circuit according to the present disclosure avoids a power loss, thereby reducing the power consumption of the whole circuit.

主权项

1. A shift register unit circuit, comprising: a trigger signal end, a first clock end, a second clock end, a reset end, a gate output end, a low level end, a storage capacitor, a reset module, a first pull-down module, a second pull-down module, a charging module, and an output control module, wherein,
the charging module has a first input end and a first control end connected to the trigger signal end, and a first output end connected to a first end of the storage capacitor to charge the storage capacitor when the trigger signal end is at a high level; and a second input end connected to the first end of the storage capacitor, a second control end connected to the first clock end, and a second output end connected to the trigger signal end to pull a voltage at the first end of the storage capacitor to a low level when the first clock end is at a high level and the trigger signal end is at a low level; the output control module has an input end connected to the second clock end, a control end connected to the first end of the storage capacitor, and an output end connected to the gate output end, to output a high level signal at the second clock end to the gate output end when the first end of the storage capacitor is at a high level, so that the gate output end is at a high level; and the storage capacitor has a second end connected to the gate output end; the first pull-down module has a first control end connected to the first clock end, a first input end connected to the gate output end, a first output end connected to the low level end, a second control end connected to the first end of the storage capacitor, a second input end connected to the first clock end, and a second output end connected to the low level end; and the second pull-down module has an input end connected to the gate output end, a control end connected to an intermediate control node of the first pull-down module, and an output end connected to the first end of the storage capacitor, wherein the first pull-down module is configured to pull a voltage at the gate output end to a low level, and trigger the second pull-down module through the intermediate control node to pull voltages at both ends of the storage capacitor to a low level when the first end of the storage capacitor is at a low level; and the reset module has an input end connected to the first end of the storage capacitor, a control end connected to the reset end, and an output end connected to the gate output end, to pull the voltages at both ends of the storage capacitor to a low level under the control of the reset end.