发明名称 |
Bitline voltage regulation in non-volatile memory |
摘要 |
Systems and methods are provided to minimize write disturb conditions in an untargeted memory cell of a non-volatile memory array. Bitline driver circuits are provided to control a ramped voltage applied both to a bitline of a target memory cell and a neighboring bitline of an untargeted memory cell. Various embodiments advantageously maintain the integrity of data stored in the untargeted memory cells by applying a controlled voltage signal to a previously floating bitline of a neighbor cell to reduce a potential difference between the source and drain nodes of the untargeted neighbor memory cell during a write operation at a target memory cell. In another embodiment, an increased source bias voltage is applied on a “source” bitline of the target cell during the ramping of the drain bias voltage and then reduced to a ground or near ground potential during the write operation. |
申请公布号 |
GB2519884(B) |
申请公布日期 |
2016.10.05 |
申请号 |
GB20150001977 |
申请日期 |
2013.07.29 |
申请人 |
Cypress Semiconductor Corporation |
发明人 |
Evrim Binboga |
分类号 |
G11C16/34;G11C16/10;G11C16/24 |
主分类号 |
G11C16/34 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|