| 摘要 |
A memory cell (10) includes a floating gate transistor (FGT1), a word line transistor (WLT1) , a first capacitance element (110), a second capacitance element (120), and a first voltage passing device (130). The floating gate transistor (FGT1) has a first terminal for receiving a bit line signal (BL), a second terminal, and a floating gate. The word line transistor (WLT1) is coupled to the floating gate transistor (FGT1), receives a third voltage (GND), and is controlled by a word line signal (WL). The first capacitance element (110) is coupled to the first voltage passing device (130) and the floating gate, and receives a first control signal (CS1). The voltage passing device (130) outputs a second voltage (VZ) during an inhibit operation and a first voltage (VPP) during a program operation or an erase operation. With the voltage passing device, the reading time and the power consumption can both be reduced. |
