发明名称 メモリ制御装置、情報処理装置、及びメモリ制御方法
摘要 Accesses to a memory divided into a plurality of units of operation are controlled. First and second units of operation from among the plurality of units of operation constitute a memory mirror. A reception circuit receives a plurality of read requests including bank identification information corresponding to both a first bank included in a first unit of operation and a second bank included in a second unit of operation, respectively. A determination circuit determines an access target of each read access so that the plurality of read accesses based on the plurality of read requests are made to the first and second units of operation alternately. The control circuit controls each read request so that each read access is made to a unit of operation determined as the access target.
申请公布号 JP6003451(B2) 申请公布日期 2016.10.05
申请号 JP20120207347 申请日期 2012.09.20
申请人 富士通株式会社 发明人 原 聡二
分类号 G06F11/16 主分类号 G06F11/16
代理机构 代理人
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