发明名称 Instruction and Logic for Speculative Request Support for Prefetching
摘要 A processor includes a core and a prefetcher. The prefetcher includes logic to issue a request for data including a requested prefetch. The core includes logic to receive an indication of the request, determine whether the request is for a restricted region of memory, and, based upon whether the request is for the restricted region of memory, allow or deny the request.
申请公布号 US2016283232(A1) 申请公布日期 2016.09.29
申请号 US201514671569 申请日期 2015.03.27
申请人 Sade Raanan;Carlson Ryan L.;Novakovsky Larisa;Hallnor Erik G.;Rajwar Ravi;Dementiev Roman 发明人 Sade Raanan;Carlson Ryan L.;Novakovsky Larisa;Hallnor Erik G.;Rajwar Ravi;Dementiev Roman
分类号 G06F9/30;G06F9/38 主分类号 G06F9/30
代理机构 代理人
主权项 1. A processor, comprising: a prefetcher including a first logic to issue a request for data, the request including a requested prefetch of the data; and a core, including: a second logic to receive an indication of the request;a third logic to determine whether the request is for a region of restricted memory; anda fourth logic to, based upon whether the request is for the live region of the execution transaction, allow or deny the request.
地址 Kibbutz Gvat IL