Memory Controller For Multi-Level System Memory With Coherency Unit

摘要

An apparatus is described that includes a memory controller having an interface to couple to a multi-level system memory. The memory controller also includes a coherency buffer and coherency services logic circuitry. The coherency buffer is to keep cache lines for which read and/or write requests have been received. The coherency services logic circuitry is coupled to the interface and the coherency buffer. The coherency services logic circuitry is to merge a cache line that has been evicted from a level of the multi-level system memory with another version of the cache line within the coherency buffer before writing the cache line back to a deeper level of the multi-level system memory if at least one of the following is true: the another version of said cache line is in a modified state; the memory controller has a pending write request for the cache line.

主权项

1. A method, comprising:
performing the following with a memory controller coupled to a multi-level system memory: receiving a read request for a cache line; referring to a coherency buffer within said memory controller for said cache line; issuing a read request to a level of said multi-level system memory in response to said cache line not being found in said coherency buffer; populating said coherency buffer with said cache line and servicing said request by providing said cache line.