| 摘要 |
PROBLEM TO BE SOLVED: To provide a digital PLL circuit that can detect a phase difference with higher precision than normal precision determined by an operation clock.SOLUTION: A PLL circuit for generating and outputting a generation clock synchronized with an external clock as an input clock signal of a substantially fixed period has a multi-phase clock generator for generating multi-phase clocks of n containing an operation clock, a frequency number generator for outputting a frequency number on the basis of a phase difference signal, an oscillator for generating and outputting a clock which oscillates at the frequency corresponding to the frequency number, and a phase comparator for measuring a first timing as a time of rising or the like of the input external clock on the basis of the multi-phase clock, calculating a second timing as a time of rising or the like of the generated clock on the basis of the frequency number and an overflow residual value as an accumulation value when the clock is generated in the oscillator, and outputting a phase difference signal representing the time difference between the first timing and the second timing.SELECTED DRAWING: Figure 1 |
