发明名称 DATA SERIALIZER
摘要 A serializer circuit may include a recovery circuit, an adjusting circuit, and a multiplexer circuit. The recovery circuit may be configured to receive a first data signal at a first frequency, to generate a first clock signal at the first frequency using the first data signal, and to retime the first data signal based on the first clock signal to generate a retimed first data signal. The adjusting circuit may be configured to receive a second data signal and retime the second data signal based on the first clock signal to generate a retimed second data signal. The multiplexer circuit may be configured to multiplex the retimed first data signal and the retimed second data signal.
申请公布号 EP3072249(A1) 申请公布日期 2016.09.28
申请号 EP20140806154 申请日期 2014.11.18
申请人 FINISAR CORPORATION 发明人 NGUYEN, THE'LINH;CASE, DANIEL, K.
分类号 H04J3/04;H03L7/08;H03M9/00;H04L25/14 主分类号 H04J3/04
代理机构 代理人
主权项
地址