发明名称 |
SDRAMインターフェイスを有するDRAM、フラッシュメモリ混載メモリモジュール |
摘要 |
When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal. |
申请公布号 |
JP5996781(B2) |
申请公布日期 |
2016.09.21 |
申请号 |
JP20150507793 |
申请日期 |
2013.03.27 |
申请人 |
株式会社日立製作所 |
发明人 |
植松 裕;村岡 諭;大坂 英樹;柴田 正文;福村 裕祐;渡辺 聡;柿田 宏;出居 昭男;上野 仁;尾野 孝之;宮川 貴志;内藤 倫典;隅倉 大志;福田 裕一 |
分类号 |
G06F12/06;G06F12/00;G11C5/00 |
主分类号 |
G06F12/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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