| 摘要 |
A successive approximation register,SAR, analog to digital converter, ADC, circuit receiving an analog input signal (Vin) and operating in a sample phase and a conversion phase following the sample phase to generate a digital output signal (D 0 ) , comprising:
a plurality of capacitors(C 0 , ..., C N-1 ) coupled to a summing node (N20), wherein before the conversion phase, a target capacitor (C j ) among the plurality of capacitors is coupled to a direct current voltage (q*VR) and the other capacitors among the plurality of capacitors are coupled to the analog input signal;
a comparator (20) having an input terminal coupled to the summing node, wherein in the conversion phase, the comparator performs a comparison operation to a summing voltage at the summing node; and
a logic unit (21) having a plurality of weighting values corresponding to the plurality of capacitors respectively and generating the digital output signal according to the weighting values and a comparison result of the comparison operation,
wherein the DC voltage has a first voltage level or a second voltage level different from the first voltage level according to a random sequence (q),
an extraction and compensation unit (11,110) receiving the digital output signal,
wherein the extraction and compensation unit performs a correlation operation (40) to the digital output signal with the random sequence and further performs a low-pass-filtering operation(41) to the digital output signal to generate a calibrated weighting value (Wj), and
wherein the extraction and compensation unit corrects the digital output signal based on the weighting value of the target capacitor and
wherein the weighting value of the target capacitor is calibrated according to the digital output signal and the random sequence. |
