Multi-processor synchronization using time base counters

摘要

A multi-processor system includes a first processor 52a that includes a first time base counter 58a that outputs a first time base count, a second processor 52b that includes a second time base counter 58b that outputs a second time base count, and a communication bus 54. The first and second processors exchange the first and second time base counts on the communication bus. The first and second processors determine a skew based upon a difference between the first and second time base counts, and the first and second processors synchronize with each other based upon the skew.