发明名称 回路設計支援装置及び回路設計支援方法及びプログラム
摘要 PROBLEM TO BE SOLVED: To cause two or more associated buffers used for an association between a write access array and a read access array having a common array name to be generated in high-level synthesis.SOLUTION: A processing section 3 inputs a behavioral description code for which a write access array write-accessed and a read access array read-accessed are used. Further, the processing section 3 inputs a buffer designation table by which conditions for the write access array and the read access array for causing two or more associated buffers to be generated in high-level synthesis are defined. Furthermore, the processing section 3 extracts the write access array and the read access array having a common array name from the behavioral description code and designates the write access array and the read access array to generate the two or more associated buffers in the high-level synthesis when the conditions defined by the buffer designation table for the extracted write access array and the extracted read access array are satisfied.
申请公布号 JP5979965(B2) 申请公布日期 2016.08.31
申请号 JP20120108307 申请日期 2012.05.10
申请人 三菱電機株式会社 发明人 山本 亮
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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