发明名称 回路の製造方法
摘要 A method for manufacturing an integrated circuit includes the steps of: forming above an upper surface of a substrate (5) at least one dielectric layer (15) extending on an underlying surface (12), the dielectric layer (15) having an upper surface (25) and a flank (40) extending between the upper surface and the underlying surface (12); and forming an electrical structure (70) in one piece in an electrically conducting material including a structural element (75) extending on the upper surface (25) of the dielectric layer (15) and an interconnection element (80) extending from the structural element (75) along the flank (40) as far as the underlying surface. The flank has a height of more than 10 mum, and the electrical structure is formed by depositing the electrically conducting material by simultaneously depositing the structural element on the upper surface of the dielectric layer and the interconnection element on the flank.
申请公布号 JP5982381(B2) 申请公布日期 2016.08.31
申请号 JP20130532251 申请日期 2011.10.05
申请人 サントル ナスィオナル ド ラ ルシェルシュ スィアンティフィク(セ.エン.エル.エス.) 发明人 アヤド・ガナム;ダヴィッド・ブリエ;モニク・ディラン;クリストフ・ヴィアロン;ティエリー・パラ
分类号 H01L21/768;H01L23/522 主分类号 H01L21/768
代理机构 代理人
主权项
地址