发明名称 SAMPLE-RATE CONVERSION IN A MULTI-CLOCK SYSTEM SHARING A COMMON REFERENCE
摘要 A method comprises determining a reference ratio based on a first division ratio of a first phase-locked loop (PLL) and a second division ratio of a second PLL, and converting a first discrete sequence to a second discrete sequence based on a sequence of multiples of the reference ratio. The first and second PLLs operate under a locked condition and share a common reference oscillator. An apparatus includes comprises a clock generator including first and second phase-locked loops (PLLs) and configured to generate first and second clock signals, respectively, and a sample-rate converter configured to convert a first discrete sequence to a second discrete sequence based on a sequence of multiples of a reference ratio. The reference ratio is determined based on a first division ratio of the first PPL and a second division ratio of the second PLL.
申请公布号 EP3061187(A1) 申请公布日期 2016.08.31
申请号 EP20140855580 申请日期 2014.10.23
申请人 MARVELL WORLD TRADE LTD. 发明人 WINOTO, RENALDI
分类号 H03L7/06;H03L7/07 主分类号 H03L7/06
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