发明名称 MEMORY CONTROL METHOD AND SYSTEM
摘要 Memory access contention by plural devices is prevented. A multi-core processor system (100) at time t3 designated by reference numeral (103) allocates processing executed by an app (#0) to a GPU (106) and allocates processing executed by an app (#1) to a CPU (#0). The multi-core processor system (100) then controls a memory controller (112) so that the GPU (106) accesses a storage area (115#0) as an area for app (#0), via a port (113#0) as a port for app (#0). The multi-core processor system (100) further controls the memory controller (112) so that the CPU (#0) accesses a storage area (115#1) as an area for app (#1), via a port (113#1) that is not the port for app (#0).
申请公布号 EP2669805(A4) 申请公布日期 2016.08.31
申请号 EP20110857205 申请日期 2011.01.25
申请人 FUJITSU LIMITED 发明人 YAMAUCHI, HIROMASA;YAMASHITA, KOICHIRO;SUZUKI, TAKAHISA;KURIHARA, KOJI;OTOMO, TOSHIYA
分类号 G06F12/00;G06F9/445;G06F9/50;G06F12/02;G06F12/08;G06F12/10;G06F15/167;G11C7/10 主分类号 G06F12/00
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