| 摘要 |
A PMOS output stage (20P) and an NMOS output stage (20N) of which output impedances are controlled in accordance with impedance codes (60), a gate control part (32P) which drives output transistors held by the PMOS output stage and the NMOS output stage, and a slew rate control part (40) which generates bias voltages (42) to control driving ability of the gate control part based on an input current are included, and manufacturing variability of an input current circuit (41) generating an input current is corrected by using the impedance code (60) by the slew rate control part (40). |
