| 摘要 |
PURPOSE:To give availability to a temporary memory read fault by automatically prolonging a memory cycle when a parity error occurs. CONSTITUTION:A memory access analysis means 4 analyzes the type of the memory access of a CPU part 1. A WAIT output means 5 outputs a WAIT signal to an AND gate 6 when the type is a memory access. A parity detection means 3 inspects the presence or absence of the parity error of read data on a data bus 11, and outputs '0' at normal time to the AND gate 6, and '1' at the time of the error. When memory read is abnormal, the WAIT signal is outputted to the CPU part 1. Thus, a WAIT cycle is inserted until the error is eliminated when the error occurs, the memory cycle is expanded and a read margin increases. Thus, the occurrence of the temporary read error due to impulse noise and the lack of the margin is prevented. |
