| 摘要 |
Data processing apparatus 420 comprises: a processor configured to execute instructions, the processor having a pipelined instruction fetching unit 460 configured to fetch instructions from memory 30 during a pipeline period of two or more processor clock cycles prior to their execution; exception logic 470 configured to respond to a detected processing exception 110 having an exception type, by storing a current processor status and diverting program flow to an exception address dependent upon the exception type so as to control the instruction fetching unit to initiate fetching of an exception instruction at the exception address; and an exception cache 430 configured to cache information, for at least one of the exception types, relating to execution of the exception instruction at the exception address corresponding to that exception type and to provide the cached information to the processor in response to detection of such an exception. This may facilitate reduced branch latency in interrupt handling (Figure 7). Also claimed is an exception cache, as defined above, which comprises a flag (630 in Figure 6), associated with each exception type for which it is configured to cache information, indicating whether it holds currently valid information for that exception type. |
