发明名称 半導体集積回路
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can be achieved by a standard CMOS process capable of microfabrication and which is capable of a high-voltage operation.SOLUTION: A semiconductor integrated circuit comprises: an output buffer 30 including an output P-channel transistor 31 and an output N-channel transistor 32 which are inserted in series between a high-voltage side power supply node (VPP=10 V) and a low-voltage side power supply node (VSS=0 V); and a level shifter 40 for generating a high-voltage side logic signal having an upper limit voltage VPP=10 V and a lower limit voltage 5 V, and a low-voltage side logic signal having an upper limit voltage VD3=3 V and a lower limit voltage 0 V, from an output signal of an inverter 71 having an upper limit voltage VD3=3 V and a lower limit voltage VS=0 V, and supplying the high-voltage side logic signal and the low-voltage side logic signal to respective gates of the output P-channel transistor 31 and the output N-channel transistor 32.
申请公布号 JP5978629(B2) 申请公布日期 2016.08.24
申请号 JP20120010493 申请日期 2012.01.20
申请人 凸版印刷株式会社 发明人 浅野 正通;汐留 俊介;松田 洋行;今井 保則
分类号 H03K19/0175;H03K19/0185 主分类号 H03K19/0175
代理机构 代理人
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