| 摘要 |
A data processor comprises: a sequence of processing stages, where each stage comprises a plurality of processing elements 1, each element comprising an arithmetic logic unit, one or more input data buffers and one or more output data buffers; an interconnect 2 between each pair of stages, for conveying data values stored in the output data buffers of the processing elements in a first stage in the pair to the input data buffers of the processing elements in the next stage in the pair; and a controller, operable to specify, in respect of each processing stage, a data processing operation to be carried out by the processing elements in that stage, and to specify, in respect of each interconnect or data movement plane, a routing from one or more of the output data buffers of one or more of the processing elements of the stage from which the interconnect is receiving data to one or more of the input data buffers of one or more of the processing elements of the processing stage to which the interconnect is conveying data. A very long instruction word, VLIW 5, may specify the operations and routing along a pipeline of SIMD processing planes. |
