Methods and Apparatus for SRAM Cell Structure

摘要

An SRAM cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second CVdd node, a first and a second CVss node, at a bit line node, at a bit line bar node, at a data node and at a data bar node; and second level contacts formed on each of the first level contacts at the first and second CVdd nodes, the first and second CVss nodes, the bit line node and the bit line bar node; wherein the first level contacts formed at the data node and the data bar node do not have a second level contact formed thereon. In another embodiment, a word line is formed and bit lines and a CVdd and a CVss line are formed overlying the SRAM cell and coupled to the corresponding ones of the nodes. Methods are disclosed for forming the cell structure.

主权项

1. An apparatus, comprising:
an SRAM cell formed in a portion of a semiconductor substrate, comprising:
a latch circuit having a data node and a data bar node, a first and a second positive power supply node and a first and a second negative power supply node;a first pass gate coupled between a bit line node and the data node;a second pass gate coupled between a bit line bar node and the data bar node;first level contacts formed at the first and second power supply nodes, the first and second negative power supply nodes, the bit line node, the bit line bar node, the data node and the data bar node; and second level contacts formed on each of the first level contacts at the first and second positive power supply nodes, the first and second negative power supply nodes, the bit line node and the bit line bar node; wherein the first level contacts formed at the data node and the data bar node do not have a second level contact formed thereon.